A High-Speed and Low-Offset Dynamic Latch Comparator
نویسندگان
چکیده
منابع مشابه
A High-Speed and Low-Offset Dynamic Latch Comparator
Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide...
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The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations sh...
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In high speed ADC, speed limiting element is comparator. This paper describes a very high speed and low offset preamplifierlatch comparator. The threshold and width of the new comparator can be reduced to the mV range, the resolution and the dynamic characteristics are good. Based on TSMC 0.18um CMOS process model, simulated results show the comparator can work under ultra high speed clock freq...
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ژورنال
عنوان ژورنال: The Scientific World Journal
سال: 2014
ISSN: 2356-6140,1537-744X
DOI: 10.1155/2014/258068